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1 ? fn8215.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. X96011 temperature sensor with look up table memory and dac features ? single programmable current generator ?1.6 ma max. ?8-bit (256 step) resolution ?internally programmabl e full scale current outputs ? integrated 8-bit a/d converter ? internal voltage reference ? temperature compensation ?internal sensor ?-40c to +100c range ? 2.2c / step resolution ?eeprom look-up table ? hot pluggable ? write protection circuitry ?intersil blocklock? ?logic controlled protection ? 2-wire bus with 3 slave address bits ? 3v to 5.5v, single supply operation ? package ?14 ld tssop ? pb-free plus anneal available (rohs compliant) applications ? pin diode bias control ? rf pa bias control ? temperature compensated process control ? laser diode bias control ?fan control ? motor control ? sensor signal conditioning ? data aquisiti on applications ? gain vs. temperature control ? high power audio ? open loop temperature compensation ? close loop current, voltage, pressure, temper- ature, speed, position programmable voltage sources, electronic loads, output amplifiers, or function generator description the X96011 is a highly integrated bias controller which incorporates a digitally controlled programmable cur- rent generator, and temperature compensation using one look-up table. all functi ons of the device are con- trolled via a 2-wire digital serial interface. the temperature compensated programmable current generator varies the output current with temperature according to the contents of the associated nonvolatile look-up table. the look-up table may be programmed with arbitrary data by the user, via the 2-wire serial port, and an internal temperature sensor is used to control the output current response. pin configuration ordering information part number part marking temp range (c) package X96011v14i X96011v i -40 to 100 14 ld tssop X96011v14iz (note) X96011vi z -40 to 100 14 ld tssop (pb-free) note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. vss a2 3 4 nc nc nc vcc a0 1 10 11 9 12 7 8 scl 6 a1 2 wp 5 nc nc 13 14 i out sda tssop 14l data sheet october 25, 2005
2 fn8215.1 october 25, 2005 block diagram pin assignments tssop pin pin name pin description 1a0 device address select pin 0. this pin determines the lsb of the device address required to communicate using the 2-wire interfac e. the a0 pin has an on-chip pull-down resistor. 2a1 device address select pin 1. this pin determines the intermediate bit of the device address re- quired to communicate using the 2-wire interface. the a1 pin has an on-chip pull-down resistor. 3a2 device address select pin 2. this pin determines the msb of the device address required to com- municate using the 2-wire interface. the a2 pin has an on-chip pull-down resistor. 4vcc supply voltage. 5wp write protect control pin. this pin is a cmos compatible input. when low, write protection is enabled preventing any ?write? operation. when high , various areas of the memory can be pro- tected using the block lock bits bl1 and bl0. the wp pin has an on-chip pull-down resistor, which enables the write protection when this pin is left floating. 6scl serial clock. this is a ttl compatible input pin. this input is the 2-wire interface clock contro lling data input and output at the sda pin. 7sda serial data. this pin is the 2-wire interface data into or out of the device. it is ttl compatible when used as an input, and it is open drain when used as an output. this pin requires an external pull up resistor. 8i out current generator output. this pin sinks or sources current. the magnitude and direction of the current is fully programmable and adaptive. the resolution is 8 bits. 9nc no connect. 10 nc no connect. 11 vss ground. 12 nc no connect. 13 nc no connect. 14 nc no connect. sda scl wp 2-wire i out interface a2, a1, a0 dac adc look-up table control & status mux mux temperature sensor voltage reference X96011
3 fn8215.1 october 25, 2005 absolute maximum ratings all voltages are referred to vss. temperature under bias ................... -65c to +100c storage temperature ......... ............... -65c to +150c voltage on every pin except vcc ................ -1.0v to +7v voltage on vcc pin .............................................0 to 5.5v d.c. output current at pin sda ...................... 0 to 5 ma d.c. output current at pins iout ....................... -3 to 3ma lead temperature (soldering, 10s) .................... 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating con- ditions for extended periods ma y affect device reliability. recommended operating conditions parameter min. max. units temperature -40 +100 c temperature while writing to memory 0 +70 c voltage on vcc pin 35.5v voltage on any other pin -0.3 vcc + 0.3 v X96011
4 fn8215.1 october 25, 2005 electrical characteristics (conditions are as follows , unless otherwise specified) all typical values are for 25c ambient temperature and 5 v at pin vcc. maximum and mini mum specifications are over the recommended operating conditions. all voltages are referred to the voltage at pin vss. bi t 7 in control register 0 is ?1?, while other bits in control registers are ?0?. 400khz ttl input at scl. sda pulled to vcc through an external 2k ? resistor. 2-wire interface in ?standby? (see notes 1 and 2 below). wp , a0, a1, and a2 floating. notes: 1. the device goes into standby: 200 ns a fter any stop, except those that initia te a nonvolatile write cycle. it goes into standby t wc after a stop that initiates a nonvolatile write cycle. it also goes in to standby 9 clock cycles after any start that is not followed by the cor- rect slave address byte. 2. t wc is the time from a valid stop condition at the end of a wr ite sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. 3. this parameter is periodically sampled and not 100% tested. symbol parameter min typ max unit test conditions / notes iccstby standby current into vcc pin 2 ma iout floating, sink mode iccfull full operation current into vcc pin 6 ma 2-wire interface reading from memory, iout connected to vss, dac input bytes: ffh iccwrite nonvolatile write current into vcc pin 4 ma average from start condition until t wp after the stop condition wp : vcc, iout floating, sink mode vref unloaded. i pldn on-chip pull down current at wp , a0, a1,and a2 0120 av(wp ), v(a0), v(a1), and v(a2) from 0v to vcc v ilttl scl and sda, input low voltage 0.8 v v ihttl scl and sda, input high voltage 2.0 v i inttl scl and sda input current -1 10 a pin voltage between 0 and vcc, and sda as an input. v olsda sda output low voltage 0 0.4 v i(sda) = 2 ma i ohsda sda output high current 0 100 a v(sda) = vcc v ilcmos wp , a0, a1, and a2 input low voltage 00.2 x vccv v ihcmos wp , a0, a1, and a2 input high voltage 0.8 x vcc vcc v tsenserange temperature sensor range -40 100 c see note 3. v por power-on reset threshold voltage 1.5 2.8 v vccramp vcc ramp rate 0.2 50 mv / s v adcok adc enable minimum voltage 2.6 2.8 v see figure 8. X96011
5 fn8215.1 october 25, 2005 d/a converter characteristics (see pg. 5 for standard conditions) notes: 1. lsb is defined as divided by the resistance between r1 or r2 to vss. 2. offset dac : the offset of a dac is defined as t he deviation between the measured and ideal out put, when the dac input is 01h. it is expressed in lsb. fserror dac : the full scale error of a dac is defi ned as the deviation between the measured and ideal output, when the input is ffh. it is expressed in lsb. the offset dac is subtracted from the measured value before calculating fserror dac . dnl dac : the differential non-linearity of a dac is defined as th e deviation between the measured and ideal incremental change in the output of the dac, when the input changes by one code step. it is expressed in lsb. the meas ured values are adjusted for of fset and full scale error before calculating dnl dac . inl dac : the integral non-linearity of a dac is defined as the deviati on between the measured and ideal transfer curves, after adjust- ing the measured transfer curve for offset and full scale error. it is expressed in lsb. 3. these parameters are periodically sampled and not 100% tested. symbol parameter min typ max unit test conditions / notes ifs iout full scale current 1.56 1.58 1.6 ma dac input byte = ffh, source or sink mode, v(iout) is vcc?1.2v in source mode and 1.2v in sink mode. see notes 1 and 2. offset dac iout d/a converter offset error 1 1 lsb fserror dac iout d/a converter full scale error -2 2 lsb dnl dac iout d/a converter differential nonlinearity -0.5 0.5 lsb inl dac iout d/a converter integral nonlinearity with respect to a straight line through 0 and the full scale value -1 1 lsb visink i1 sink voltage compliance 1.2 vcc v in this range the current at i1 vary < 1% visource i1 source voltage compliance 0 vcc - 1.2 v in this range the current at i1 vary < 1% i over i1 overshoot on d/a converter data byte transition 0 a dac input byte changing from 00h to ffh and vice versa, v(i1) is vcc - 1.2v in source mode and 1.2v in sink mode. see note 3. i under i1 undershoot on d/a converter data byte transition 0 a t rdac i1 rise time on d/a converter data byte transition; 10% to 90% 530 s tco i1i2 temperature coefficient of output current iout 200 ppm/c see figure 5. 2 3 v(vref) 255 x [] X96011
6 fn8215.1 october 25, 2005 a/d converter characteristics (see pg. 5 for standard conditions) notes: 1. ?lsb? is defined as v(vref)/255, ?full scale? is defined as v(vref). 2. offset adc : for an ideal converter, the first transition of its tr ansfer curve occurs at above zero. offset error is the amount of deviation between the measured fi rst transition point and the ideal point. fserror adc : for an ideal converter, the last transition of its transfer curve occurs at . full scale error is the amount of deviation between the measured last transition point and the ideal point, after subtracting the offset from the measured curve. dnl adc : dnl is defined as the difference between the ideal and the measured code transitions for successive a/d code outputs expressed in lsbs. the measured transfer curve is adjusted for offset and fullscale errors before calculating dnl. inl adc : the deviation of the measured transfer function of an a/d conver ter from the ideal transfer function. the inl error is also defined as the sum of the dnl errors starting from code 00h to the code where the inl measuremen t is desired. the measured tran s- fer curve is adjusted for offset and fullscale errors before calculating inl. 3. these parameters are periodically sampled and not 100% tested. symbol parameter min typ max unit test conditions / notes adctime a/d converter conversion time 9 ms proportional to a/d converter input voltage. this value is maximum at full scale input of a/d converter. adcfiltoff = ?1? the adc is monotonic offset adc a/d converter offset error 1 lsb see notes 1 and 2 fserror adc a/d converter full scale error 1 lsb dnl adc a/d converter differential nonlinearity 0.5 lsb inl adc a/d converter integral nonlinearity 1 lsb tempstep adc temperature step causing one step increment of adc output 0.52 0.55 0.58 c see note 3 out25 adc adc output at 25c 01110101 2 0.5 x v(vref) 255 [] 254.5 x v(vref) 255 [] X96011
7 fn8215.1 october 25, 2005 2-wire interface a.c. characteristics 2-wire interface test conditions nonvolatile write cycle timing notes: 1. cb = total capacitance of one bus line (sda or scl) in pf. 2. t wc is the time from a valid stop condition at the end of a wr ite sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. 3. the minimum frequency requirement applie s between a start and a stop condition. 4. these parameters are periodically sampled and not 100% tested. symbol parameter min typ max units test conditions / notes f scl scl clock frequency 1 (3) 400 khz see ?2-wire interface test conditions? (below), see figure 1, figure 2 and figure 3. t in (4) pulse width suppression time at inputs 50 ns t aa (4) scl low to sda data out valid 900 ns t buf (4) time the bus free before start of new transmission 1300 ns t low clock low time 1.3 1200 (3) s t high clock high time 0.6 1200 (3) s t su:sta start condition setup time 600 ns t hd:sta start condition hold time 600 ns t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 600 ns t dh data output hold time 50 ns t r (4) sda and scl rise time 20 +0.1cb (1) 300 ns t f (4) sda and scl fall time 20 +0.1cb (1) 300 ns t su:wp (4) wp setup time 600 ns t hd:wp (4) wp hold time 600 ns cb (4) capacitive load for each bus line 400 pf input pulse levels 10 % to 90 % of vcc input rise and fall times, between 10% and 90% 10 ns input and output timing threshold level 1.4v external load at pin sda 2.3k ? to vcc and 100 pf to vss symbol parameter min typ max units test conditions / notes t wc (2) nonvolatile write cycle time 5 10 ms see figure 3 X96011
8 fn8215.1 october 25, 2005 timing diagrams figure 1. bus timing figure 2. wp pin timing figure 3. non-volatile write cycle timing t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r t hd:wp scl sda in wp t su:wp clk 1 start stop scl sda t wc 8th bit of last byte ack stop condition start condition X96011
9 fn8215.1 october 25, 2005 intersil sensor conditioner product family fso = full scale output, ext = external, int = internal device description the combination of the x9601 1 functionality and inter- sil?s qfn package lowers sy stem cost, increases reli- ability, and reduces board space requirements. the on-chip programmable current generator may be independently programmed to either sink or source current. the maximum current generated is deter- mined by using an externally connected programming resistor, or by selecting one of three predefined val- ues. both current generators have a maximum output of 1.6 ma, and may be controlled to an absolute res- olution of 0.39% (256 steps / 8 bit). the current generator is driven using either an on- board temperature sensor or control registers. the internal temperature sensor operates over a very broad temperature range (-40 c to +100 c). the sen- sor output drives an 8-bit a/d converter. the six msbs of the adc output select one of 64 bytes from the non- volatile look-up table (lut). the contents of the selected lut row (8-bit wide) drives the input of an 8-bit d/a converter, which gener- ates the output current. all control and setup parameters of the X96011, including the look-up table, are programmable via the 2-wire serial port. device title features / functions internal temperature sensor external sensor input internal voltage reference vref input / ouput general purpose eeprom look up table organi- zation # of dacs fso current dac setting resistors x96010 sensor conditioner with dual look-up table memory and dacs no yes yes yes no dual bank dual ext X96011 temperature sensor with look-up table memory and dac yes no yes no no single bank single int x96012 universal sensor conditioner with dual look-up table memory and dacs yes yes yes yes yes dual bank dual ext / int X96011
10 fn8215.1 october 25, 2005 principles of operation control and status registers the control and status registers provide the user with a mechanism for changing and reading the value of various parameters of the X96011. the X96011 contains five control, one status, and several reserved registers, each being one byte wide (see figure 4). the control registers 0 through 6 are located at memory addresses 80h through 86h respectively. the status register is at memory address 87h, and the reserved registers at memory address 82h, 84h, and 88h through 8fh. all bits in control register 6 always power-up to the logic state ?0?. all bits in control registers 0 through 5 power- up to the logic state value kept in their corresponding nonvolatile memory cells. t he nonvolatile bits of a reg- ister retain their stored values even when the X96011 is powered down, then powered back up. the nonvolatile bits in control 0 through control 5 registers are all pre- programmed to the logic state ?0? at the factory, except the cases that indicate ?1? in figure 1. bits indicated as ?reserved? are ignored when read, and must be written as ?0?, if any write operation is performed to their registers. a detailed description of the function of each of the control and status register bits follows: control register 0 this register is accessed by performing a read or write operation to address 80h of memory. adc filt o ff : adc f iltering c ontrol (n on - volatile ) when this bit is ?1?, the status register at 87h is updated after every conversion of the adc. when this bit is ?0? (default), the stat us register is updated after four consecutive conversions with the same result, on the 6 msbs. nv13: c ontrol registers 1 and 3 volatility mode selection bit (n on - volatile ) when the nv13 bit is set to ?0? (default), bytes written to control registers 1 and 3 are stored in volatile cells, and their content is lost when the X96011 is powered down. when the nv13 bit is set to ?1?, bytes written to control registers 1 and 3 are stored in both volatile and nonvolatile cells, and their value doesn?t change when the X96011 is powered down and powered back up. see ?writing to control registers? on page 21. ids: c urrent g enerator d irection s elect b it (n on - volatile ) the ids bit sets the polarity of the current generator. when this bit is set to ?0? (default), the current gener- ator of the X96011 is configured as a current source. the current generator is configured as a current sink when the ids bit is set to ?1?. see figure 5. X96011
11 fn8215.1 october 25, 2005 figure 4. control and status register format byte msb lsb 80h register control 0 00 ids nv13 1adcfiltoff00 non-volatile 81h control 1 volatile or reserved reserved lda5 lda4 lda3 lda2 lda1 lda0 83h control 3 volatile or dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 non-volatile non-volatile 85h control 5 non-volatile 0 0 ddas ldas 0 0 ifso1 ifso0 86h control 6 volatile wel reserved reserved reserved reserved reserved reserved reserved 87h status volatile ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 7 6 5 4 3 21 0 name address registers in byte addresses 82h, 84h, and 88h through 8fh are reserved. direct access to the lut direct access to the dac adc output iout 0: source 1: sink control 1, 3 volatility 0: volatile 1: non- volatile direct direct access to dac access to lut 0: disabled 0: disabled 1: enabled 1: enabled r selection 00: reserved 01: low internal 10: middle internal 11: high internal (default) write enable latch 0: write disabled 1: write enabled adc 0: on 1: off filtering direction registers bits shown as 0 or 1 should alwa ys use these values for proper operation. X96011
12 fn8215.1 october 25, 2005 control register 1 this register is accessed by performing a read or write operation to address 81h of memory. this byte?s volatility is determined by bit nv13 in control register 0. lda5 - lda0: lut d irect a ccess b its when bit ldas (bit 4 in control register 5) is set to ?1?, the lut is addressed by these six bits, and it is not addressed by the output of the on-chip a/d converter. when bit ldas is set to ?0?, these six bits are ignored by the X96011. see figure 7. a value between 00h (00 10 ) and 3fh (63 10 ) may be writ- ten to these register bits, to select the corresponding row in the lut. the written value is added to the base address of the lut (90h). control register 3 this register is accessed by performing a read or write operation to address 83h of memory. this byte?s volatility is determined by bit nv13 in control register 0. dda7 - dda0: d/a d irect a ccess b its when bit ddas (bit 5 in control register 5) is set to ?1?, the input to the d/a converter is the content of bits dda7 - dda0, and it is not a row of lut. when bit ddas is set to ?0? (default) these eight bits are ignored by the X96011. see figure 6. control register 5 this register is accessed by performing a read or write operation to address 85h of memory. ifso1 - ifso0: c urrent g enerator f ull s cale o utput s et b its (n on - volatile ) these two bits are used to se t the full scale output cur- rent at the current generator pin, iout, according to the following table. the direct ion of this current is set by bit ids in control register 0. see figure 5. ldas: lut d irect a ccess s elect b it (n on - volatile ) when bit ldas is set to ?0? (default), the lut is addressed by the output of the on-chip a/d converter. when bit ldas is set to ?1?, lut is addressed by bits lda5 - lda0. ddas: d/a d irect a ccess s elect b it (n on - volatile ) when bit ddas is set to ?0? (default), the input to the d/a converter is a row of the lut. when bit ddas is set to ?1?, that input is the content of the control register 3. control register 6 this register is accessed by performing a read or write operation to address 86h of memory. i1fso1 i1fso0 i1 full scale output current 0 0 reserved (don?t use) 01 0.4ma 10 0.85 ma 11 1.3 ma (default) X96011
13 fn8215.1 october 25, 2005 wel: w rite e nable l atch (v olatile ) the wel bit controls the wr ite enable status of the entire X96011 device. this bit must be set to ?1? before any other write operation (vol atile or nonvolatile). oth- erwise, any proceeding write operation to memory is aborted and no ack is issued after a data byte. the wel bit is a volatile latch that powers up in the ?0? state (disabled). the wel bit is enabled by writing 10000000 2 to control register 6. once enabled, the wel bit remains set to ?1? until the X96011 is powered down, and then up again, or until it is reset to ?0? by writing 00000000 2 to control register 6. a write operation that modifies the value of the wel bit will not cause a change in other bits of control register 6. status register - adc output this register is accessed by performing a read opera- tion to address 87h of memory. ad7 - ad0: a/d c onverter o utput b its (r ead only ) this byte is the binary output of the on-chip digital thermometer. the output is 00000000 2 for -40c and 11111111 2 for 100c. the six msbs select a row of the lut. look-up table the X96011 memory array contains a 64-byte look-up table. the look-up table is associated to pin iout?s out- put current generator through the d/a converter. the output of the look-up table is the byte contained in the selected row. by default this byte is the input to the d/a converter driving pin iout. the byte address of the selected row is obtained by adding the look-up table base address 90h, and the appropriate row selection bits. see figure 6. by default the look-up table selection bits are the 6 msbs of the digital thermometer output. alter- natively, the a/d conver ter can be bypassed and the six row selection bits are the six lsbs of control register 1 for the lut. the selection between these options is illustrated in figure 6. current generator block the current generator pin iout is the output of the cur- rent mode d/a converter. d/a converter operation the block diagram for the d/a converter is shown in figure 5. the input byte of the d/a converter selects a voltage on the non-inverting input of an operational amplifier. the output of the amplifier drives the gate of a fet. this node is also fed back to the inverting input of the amplifier. the drain of the fet is connected to the out- put current pin (iout) via a ? polarity select? circuit block. X96011
14 fn8215.1 october 25, 2005 figure 5. d/a converter block diagram + - iout pin ids: bit vss vss ifso[1:0] low_current middle_current high_current internal select circuit polarity vcc voltage 6 in control register 0. divider dac input byte vss bits 1 and 0 in control register 5 11 10 01 reference voltage figure 6. look-up table (lut) operation dac 8 90h 90h cfh 8 lut 6 lut row out d1 d0 select ddas: bit 5 of dda[7:0] : control register 3 selection bits a d d e r 8 8 input byte control register 5 ? X96011
15 fn8215.1 october 25, 2005 by examining the block diagram in figure 5, we see that the maximum current through pin iout is set by fix- ing values for v(vref) and r. the output current can then be varied by changing the data byte at the d/a converter input. in general, the magnitude of the current at the d/a converter output pin may be calculated by: i = (v(vref) / (384 ? r)) ? n where n is the decimal representation of the input byte to the corresponding d/a converter. the value for the resistor determines the full scale out- put current that the d/a converter may sink or source. bits ifso1 and ifso0 select the full scale output cur- rent setting for iout as described in ?ifso1 - ifso0: current generator full scale output set bits (non-vol- atile)? on page 12. bit ids and in control register 0 select the direction of the currents through pins iout (see ?ids: current gen- erator direction select bit (non-volatile)? on page 10 and ?control and status register format? on page 11). d/a converter output current response when the d/a converter input data byte changes by an arbitrary number of bits, the output current changes from an intial current level (i x ) to some final level (i x + ? i x ). the transition is monotonic and glitchless. d/a converter control the data byte inputs of the d/a converters can be con- trolled in three ways: ? 1) with the a/d converter and through the look-up tables (default), ? 2) bypassing the a/d converter and directly access- ing the look-up tables, ? 3) bypassing both the a/d converter and look-up tables, and directly setting the d/a converter input byte. d1 d0 select adc ad[7:0] lut row voltage voltage input selection bits reference out lda[5:0]: control register 1 ldas: bit 4 in control register 5 6 6 status register figure 7. look-up table addressing 8 from internal temperature sensor X96011
16 fn8215.1 october 25, 2005 the options are summarized in the following tables: d/a converter access summary bit ddas is used to bypass the a/d converter and look-up table, allowing direct access to the input of the d/a converter with the byte in control register 3. see figure 6, and the descriptions of the control bits. bit ids in control register 0 select the direction of the current through pin iout. see figure 5, and the descriptions of the control bits. power-on reset when power is applied to the vcc pin of the X96011, the device undergoes a strict sequence of events before the current outputs of the d/a converters are enabled. when the voltage at vcc becomes larger than the power-on reset threshold voltage (v por ), the device recalls all control bits from non-volatile memory into volatile registers. next, the analog circuits are pow- ered up. when the voltage at vcc becomes larger than a second voltage threshold (v adcok ), the adc is enabled. in the default case, after the adc performs four consecutive conversions with the same exact result, the adc output is used to select a byte from the look-up table. the byte becomes the input of the dac. during all the previous sequence the input of the dac is 00h. if bit adcfiltoff is ?1?, only one adc conversion is necessary. bit ddas an d ldas, also modify the way the dac is accessed the first time after power-up, as described in ?control register 5? on page 12. the X96011 is a hot pluggable device. voltage dis- trubances on the vcc pin are handled by the power-on reset circuit, allowing proper operation during hot plug- in applications. ldas ddas control source 0 0 a/d converter through lut (default) 1 0 bits lda5 - lda0 through lut x 1 bits dda7 - dda0 ?x? = don?t care condition (may be either ?1? or ?0?) figure 8. d/a converter power-on reset response i x i x x 10% adc time current time time vcc v adcok 0v voltage X96011
17 fn8215.1 october 25, 2005 serial interface serial interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the mast er always initiates data transfers, and provides the clock for both transmit and receive operations. the X96011 operates as a slave in all applications. serial clock and data data states on the sda line can change only while scl is low. sda state changes while scl is high are reserved for indicating start and stop condi- tions. see figure 10. on power-up of the X96011, the sda pin is in the input mode. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda while scl is high. the device contin uously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met. see figure 9. serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see figure 9. serial acknowledge an ack (acknowledge), is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data. see figure 11. the device responds with an ack after recognition of a start condition followed by a valid slave address byte. a valid slave address byte must contain the device type identifier 1010, and the device address bits matching the logic state of pins a2, a1, and a0. see figure 13. if a write operation is selected, the device responds with an ack after the receipt of each subsequent eight-bit word. in the read mode, the device transmits eight bits of data, releases the sda line, and then monitors the line for an ack. the device cont inues transmitting data if an ack is detected. the device terminates further data transmissions if an ack is not detected. the master must then issue a stop condition to place the device into a known state. the X96011 acknowledges all incoming data and address bytes except: 1) the ?slave address byte? when the ?device identifier ? or ?device address? are wrong; 2) all ?data bytes? when the ?wel? bit is ?0?, with the exception of a ?data byte? addresses to loca- tion 86h; 3) ?data bytes? following a ?data byte? addressed to locations 80h, 85h, or 86h. X96011
18 fn8215.1 october 25, 2005 figure 9. valid start and stop conditions figure 10. valid data changes on the sda bus figure 11. acknowledge response from receiver scl sda start stop scl sda data stable data change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master X96011
19 fn8215.1 october 25, 2005 X96011 memory map the X96011 contains a 80 byte array of mixed volatile and nonvolatile memory. this array is split up into two distinct parts, namely: (refer to figure 12.) ? look-up table (lut) ? control and status registers figure 12. X96011 memory map the control and status registers of the X96011 are used in the test and setup of the device in a system. these registers are realized as a combination of both volatile and nonvolatile memory. these registers reside in the memory locations 80h through 8fh. the reserved bits within registers 80h through 86h, must be written as ?0? if writ ing to them, and should be ignored when reading. register bits shown as 0 or 1, in figure 4, must be written with the indicated value if writing to them. the reserved registers, 82h, 84h, and from 88h through 8fh, must not be written, and their content should be ignored. the lut is realized as nonvolatile eeprom, and extend from memory locations 90h?cfh. this lut is dedicated to storing data solely for the purpose of set- ting the outputs of current generators i out . all bits in the lut are preprogrammed to ?0? at the factory. addressing protocol overview all serial interface operations must begin with a start, followed by a slave address byte. the slave address selects the X96011, and specifies if a read or write operation is to be performed. it should be noted that the write enable latch (wel) bit must first be set in order to perform a write opera- tion to any other bit. (see ?wel: write enable latch (volatile)? on page 13.) al so, all communication to the X96011 over the 2-wire serial bus is conducted by sending the msb of each byte of data first. the memory is physically realized as one contiguous array, organized as 5 pages of 16 bytes each. the X96011 2-wire protocol provides one address byte. the next few sections explain how to access the different areas for reading and writing. figure 13. slave address (sa) format address size 64 bytes 16 bytes 80h 8fh 90h cfh look-up table (lut) control & status registers sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read or sa4 slave address bit(s) description sa7 - sa4 device type identifier sa3 - sa1 device address sa0 read or write operation select r/w 1010 address device as0 as1 as2 write X96011
20 fn8215.1 october 25, 2005 slave address byte following a start condition, the master must output a slave address byte (refer to figure 13.). this byte includes three parts: ? the four msbs (sa7 - sa4) are the device type identifier, which must always be set to 1010 in order to select the X96011. ? the next three bits (sa3 - sa1) are the device address bits (as2 - as0). to access any part of the X96011?s memory, the val ue of bits as2, as1, and as0 must correspond to the logic levels at pins a2, a1, and a0 respectively. ? the lsb (sa0 ) is the r/w bit. this bit defines the operation to be performed on the device being addressed. when the r/w bit is ?1?, then a read operation is selected. a ?0? selects a write operation (refer to figure 13.) nonvolatile write acknowledge polling after a nonvolatile write command sequence is cor- rectly issued (including the final stop condition), the X96011 initiates an internal high voltage write cycle. this cycle typically requires 5 ms. during this time, any read or write command is ignored by the X96011. write acknowledge polling is used to deter- mine whether a high volta ge write cycle is completed. during acknowledge polling, the master first issues a start condition followed by a slave address byte. the slave address byte cont ains the X96011?s device type identifier and device address. the lsb of the slave address (r/w ) can be set to either 1 or 0 in this case. if the device is busy within the high voltage cycle, then no ack is returned. if the high voltage cycle is completed, an ack is returned and the master can then proceed with a new read or write operation. (refer to figure 14.). byte write operation in order to perform a byte write operation to the mem- ory array, the write enable latch (wel) bit of the con- trol 6 register must first be set to ?1?. (see ?wel: write enable latch (volatile)? on page 13.) for any byte write operation, the X96011 requires the slave address byte, an address byte, and a data byte (see figure 15). after each of them, the X96011 responds with an ack. the master then terminates the transfer by generating a stop condition. at this time, if all data bits are volatile, t he X96011 is ready for the next read or write operation. if some bits are nonvolatile, the X96011 begins the internal wr ite cycle to the nonvolatile memory. during the internal nonvolatile write cycle, the X96011 does not respond to any requests from the master. the sda output is at high impedance. writing to control bytes which are located at byte addresses 80h through 8fh is a special case described in the section ?writing to control registers? . page write operation the 80-byte memory array is physically realized as one contiguous array, organized as 5 pages of 16 bytes each. a ?page write? operation can be per- formed to any of the four lut pages. in order to per- form a page write operation, the write enable latch (wel) bit in control register 6 must first be set (see ?wel: write enable latch (volatile)? on page 13.) a page write operation is in itiated in the same manner as the byte write operation; but instead of terminating the write cycle after the firs t data byte is transferred, the master can transmit up to 16 bytes (see figure 16). after the receipt of each byte, the X96011 responds with an ack, and the internal byte address counter is incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to the first byte of the same page. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes no continue normal read or write command sequence proceed yes complete. continue command sequence. high voltage issue stop figure 14. acknowledge polling sequence X96011
21 fn8215.1 october 25, 2005 for example, if the master writes 12 bytes to a 16-byte page starting at location 11 (decimal), the first 5 bytes are written to locations 11 through 15, while the last 7 bytes are written to locations 0 through 6 within that page. afterwards, the address counter would point to location 7. if the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time (see figure 17). the master terminates the loading of data bytes by issuing a stop condition, wh ich initiates the nonvola- tile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. a page write operation cannot be performed on the page at locations 80h through 8fh. next section describes the special cases within that page. writing to cont rol registers the bytes at locations 80h, 81 h, 83h, 85h, and 86h are written using byte write operations. they cannot be written using a page write operation. registers control 1 and 3 have a nonvolatile and a vol- atile cell for each bit. at power-up, the content of the nonvolatile cells is automatic ally recalled and written to the volatile cells. the content of the volatile cells con- trols the X96011?s functionality. if bit nv13 in the con- trol 0 register is set to ?1?, a write operation to these registers writes to both the volatile and nonvolatile cells. if bit nv13 in the control 0 regi ster is set to ?0?, a write operation to these registers only writes to the volatile cells. in both cases the newly written values effectively control the X96011, but in the second case, those val- ues are lost when the part is powered down. if bit nv13 is set to ?0?, a byte write operation to con- trol registers 0 or 5 causes the value in the nonvolatile cells of control registers 1 and 3 to be recalled into their corresponding volatile cells, as during power-up. this doesn?t happen when the wp pin is low, because write protection is enabled. it is generally recommended to configure control registers 0 and 5 before writing to control registers 1 or 3. a ?byte write? operation to control register 1 or 3, causes the value in the nonvolatile cells of the other to be recalled into the corresponding volatile cells, as during power-up. when reading either of the c ontrol registers 1 or 3, the data bytes are always the content of the correspond- ing nonvolatile cells, even if bit nv13 is ?0? (see ?con- trol and status register format?). s t a r t s t o p slave address address byte data byte a c k signals from the master signals from the slave a c k 1 0 1 00 a c k write signal at sda figure 15. byte write sequence 2 < n < 16 signals from the master signals from the slave signal at sda s t a r t slave address address byte a c k a c k 1 0 1 00 data byte (1) s t o p a c k a c k data byte (n) write figure 16. page write operation X96011
22 fn8215.1 october 25, 2005 read operation a read operation consist of a three byte instruction followed by one or more data bytes (see figure 18). the master initiates the ope ration issuing the following sequence: a start, the slave address byte with the r/w bit set to ?0?, an address byte, a second start, and a second slave address byte with the r/w bit set to ?1?. after each of the three bytes, the X96011 responds with an ack. then the X96011 transmits data bytes as long as th e master responds with an ack during the scl cycle following the eigth bit of each byte. the master terminates the read operation (issuing a stop condition) following the last bit of the last data byte (see figure 18). the data bytes are from the memory location indicated by an internal pointer. this pointer initial value is deter- mined by the address byte in the read operation instruc- tion, and increments by one during transmission of each data byte. after reaching the memory location cfh a stop should be issued. if the read operation continues the output bytes are unpredictable. if the byte address is set between 00h and 7fh, or higher than cfh, the output bytes are unpredictable. a read operation internal pointer can start at any memory location from 80h through cfh, when the address byte is 80h through cfh respectively. when reading any of the contro l registers 1, 2, 3, or 4, the data bytes are always the content of the corre- sponding nonvolatile cells, even if bit nv13 is "0" (see ?control and status register format?). data protection there are three levels of data protection designed into the X96011: 1- any write to the device first requires setting of the wel bit in control 6 register; 2- the write protection pin disables any writing to the X96011; 3- the proper clock count, data bit sequence, and stop condition is required in order to start a nonvol- atile write cycle, otherwise the X96011 ignores the write operation. wp : write protection pin when the write protection (wp ) pin is active (low), any write operations to the X96011 is disabled, except the writing of the wel bit. 5 bytes 7 bytes address = 6 5 bytes address pointer address = 15 address = 11 ends up here address = 7 address = 0 figure 17. example: writing 12 bytes to a 16-byte page starting at location 11. signals from the master signals from the slave signal at sda s t a r t slave address with r/w = 0 address byte a c k a c k 1 0 1 00 s t o p a c k 1 1 1 00 slave address with r/w = 1 a c k s t a r t last read data byte first read data byte a c k figure 18. read sequence X96011
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8215.1 october 25, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package code v14 see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) X96011

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